Thousand Parsec: Mail Archives

> 
> Actually that is rather odd. You shouldn't be getting bus errors on an
> Intel platform as it can do non-aligned accesses.

Umm.. Only if the Unaligned bit is set in the flags register.  Any OS
designed with half a clue or an application writer with half a clue and
some knowledge of CPU usage will turn that bit off.

Apple turn it off by default I do believe (god bless them).  The CPU
itself boots with it off ;-)  

Unaligned loads are handled by microcode BTW, they actually expand to
two (independent) loads, two shifts and a register copy.  They are one
of the reasons intel CPUs need stupid guarantees on TLB entries (the
last _NINE_ entries are never flushed).

> It will be interesting to find out what is going wrong.

/me notes it's probably unaligned access after a string.

	nash